The Integrated Circuit (IC) technology has developed following the Moore law for more than 40 years. Specifically, ICs have their feature sizes continuously scaled down, integration densities continuously improved, and functions increasingly enhanced. Currently, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) already have their feature sizes scaled into the range of sub-50 nanometers. With the continuous scaling of the feature sizes, if a conventional gate of poly-silicon is adopted, then the poly-silicon will encounter more and more serious depletion effects and thus have its resistance increased. Further, PMOS devices will exhibit more significant Boron punch-through phenomenon. All those obstacles significantly prevent the device performances from being further improved. To overcome the above difficulties, the industry starts to replace the conventional gate arrangement of silicon oxide/poly-silicon with a gate arrangement of high dielectric constant (high-K) gate dielectric/metal gate.
In the manufacture of semiconductor devices having the high-K gate dielectric/metal gate arrangement, conventionally there are two types of processes. One is the “gate first” process, and the other is the “gate last” process. The gate first process is similar to the convention CMOS process, where a metal gate is first manufactured and then a source and a drain are manufactured. The gate first process is simple, and is compatible with the conventional CMOS process. More specifically, some processes of the conventional CMOS process can be used also in the gate first process, which facilitates reducing of the cost. However, the gate first process still has some disadvantages which are hard to be overcome. First, there is a large possibility that the metal gate is penetrated by ions which are to be implanted into the source and the drain, so that a resultant device will have its electrical characteristics impacted. Second, a high-temperature thermal treatment for activating source/drain purities will significantly impact the work function of the metal gate. Specifically, most of materials for the metal gate have their work functions shift to the center of their respective forbidden bands after a high-temperature annealing treatment, so that the resultant device will have its performance degraded. The gate last process is also called the Damascus process. In the gate last process commonly used in the world, an arrangement of high-K gate dielectric/sacrificial gate is first manufactured. The sacrificial gate is removed by a planarization process after processes for source/drain implantation and activation are completed, to form a gate trench, into which a metal gate is deposited instead, resulting in a semiconductor device having the high-K gate dielectric/metal gate arrangement. The gate last process is advantageous in that the metal gate is formed after the annealing process for source/drain activation and thus will not have its characteristics impacted by the high-temperature process. As a result, the resultant device will exhibit high reliability and consistency, which facilitates manufacturing high-performance semiconductor devices having the high-K gate dielectric/metal gate arrangement and circuits having the same. However, the gate last process still have some disadvantages. For example, in the process of removing the sacrificial gate, the underlying high-K gate dielectric is prone to be damaged, so that the reliability of the high-K gate dielectric is reduced.